There are several common serial communication standards currently available, including USB (Universal Serial Bus) 1.1 that provides communication speeds up to 12 Mbps (Million bits per second), FireWire (IEEE 1394) that operates at 400 Mbps, and USB 2.0 that operates at a maximum of about 480 Mbps. The operational speeds of these standards have increased over time. For example, the speed of USB 2.0 versus USB 1.1 illustrates an improvement of over 40 times. State of the art optical networks used in data communications and telecommunications operates at bit rates up to 40 Gbps (billion bits per second).
Generally, serial communication includes a transmitter and a receiver. The transmitter encodes or modulates a lower speed parallel data bus into a higher speed serial data stream that is then placed on a communication media. The serial data stream travels on the communication media and is then obtained from the media by the receiver. The serial data stream is then processed by the receiver in order to decode or recover the original data and de-serialize the resulting data into a duplicate parallel data bus.
Several techniques exist to encode the serial data and many signaling approaches can be used to transmit the data. Encoding techniques are used to embed a guaranteed density of transitions in the data and to facilitate reconstruction of the parallel data bus at the receiver. An example of these encoding techniques is 8b-10b encoding used on the physical layer in Gigabit Ethernet, PCI-Express, Fibre Channel, and 1394. Another encoding method is referred to as scrambling, which is used in SONET (Synchronous Optical NETwork). At the lowest level, the signaling approach can be as simple as NRZ (non-return to zero) binary, where 0 bit is encoding as one voltage level and a 1 bit is encoding at a different voltage level as illustrated in FIG. 1, and designated at reference numeral 100. Another commonly employed serial encoding/decoding scheme is (Non-Return-to-Zero Inverted) encoded and bit stuffed.
NRZI is a data transmission method in which the polarity of the bit is reversed whenever a 0 bit is encountered, and a static voltage level is transmitted whenever a 1 bit is encountered as illustrated in FIG. 1, and designated at reference numeral 110. NRZI thus uses the presence or absence of a transition to signify a bit (indicating a logical 0 by inverting the state). Combined with bit-stuffing, where an extra 0 bit is inserted after every six consecutive 1 bits, this data encoding causes a guaranteed transition every 7 bit times when a data payload would be all 1 bits. Every transition gives the CDR circuit phase information that it uses to align its recovered clock to the phase of the incoming data. The greater the frequency of transitions, the less phase error accumulates between the recovered clocks and the incoming data which is to be expected caused by frequency offset between the clock used to transmit the data and the recovered clock. Finally, the data can be transmitted using a multi-level signaling approach where multiple bits are encoded as multiple data levels and transmitted at a lower data rate. For example, if two bits are to be transmitted simultaneously at one half the equivalent data rate as the binary approach, four voltage levels can be assigned to the various bit combinations 00, 01, 10, and 11.
The structure of the data stream follows a specific communications protocol, which defines the rules for sending a block of data (each known as a Protocol Data Unit (PDU)) (e.g., 150 of FIG. 2) from one node in a network to another node. The exchanged PDUs comprises three parts: a sync sequence 160, a packet payload (also known as a Service Data Unit (SDU)) 170, and an End of Packet (EOP) 180. The protocol does not define or constrain the data carried in the payload portion 170 of the data block. The protocol does, however, specify the format of the sync sequence.
The incoming data stream may be at a different frequency or may exhibit wander from the receiving system. Each side of a communications link uses a reference clock that can vary from an ideal frequency within a +/− delta range as limited by a ppm tolerance value defined in a respective industry standard. Often, the source and receive frequencies are different. Regardless of the relative source and destination frequencies, the incoming data stream also exhibits all jitter components of an electrical transmission over a bandwidth limited media (e.g., data dependent cycle to cycle jitter).
Several types of clock recovery circuits exist. These include linear (also known as conventional) and phase interpolator based binary clock and data recovery. Any clock and data recovery (CDR) circuit attempts to recover the original transmitting clock despite these variations in reference frequencies or signal degradation due to jitter. A conventional CDR circuit attempts to recover the clock and data by utilizing a phase detector (PD) or alternatively a phase-frequency detector (PFD) to drive a charge pump followed by a loop filter and a voltage controlled oscillator (VCO) in a phase locked loop (PLL). The phase detector detects the absolute timing error between the current recovered clock and the timing of the ideal clock and together with the charge pump, generates an error signal proportional to the size of the timing error. This error signal is filtered using a loop filter and used to drive the VCO. These conventional linear techniques use an analog PLL, which due to variations in the transition density in the incoming data and variations in the manufacturing process, has a bandwidth, tracking capability, and frequency acquisition range that is not tightly controlled.
A phase interpolator based clock recovery system recovers the clock by examining the sign of the phase error between the current recovered clock and the data. If the recovered clock is too early, the clock recovery system delays the clock. If the recovered clock is too late, the clock is advanced.
In a conventional CDR, the capture range of the PLL and/or VCO used is typically narrow, and has a disadvantage of limiting the tracking capability (or bandwidth) of the CDR circuit, particularly when a wide range of data rates is anticipated. The analog types require many special analog components which can be difficult to implement in integrated circuit devices, and when not carefully designed may not function properly under all conditions.
As in any CDR circuit, an interpolator based CDR attempts to position the recovered clock at the center of each bit time of an incoming data stream. By sampling each bit at the center and transition point (i.e. ½ of a bit time from the center) and examining the signs of the center and transition samples, it is possible to derive whether the recovered clock is early or late with respect to the serial data stream. When a decision of early/late is made, the interpolator then makes a discrete step to either advance or retard the phase of the output clocks in an attempt to properly align the clock and data. Contrary to a conventional CDR circuit, where the size of the phase update is related to the magnitude of the phase error, the phase update from an interpolator CDR is typically the same regardless of the phase error magnitude. This can be detrimental to the integrity of the recovered clocks if the early/late decision is actually incorrect due to jitter in the incoming data or the recovered clock. In order to minimize the possibility of making an incorrect phase update, an interpolator based CDR will typically collect transition and center samples from multiple bit periods, calculate whether each clock edge was early or late, then calculate whether on average the clocks were early or late prior to making any updates in the phase of the recovered clock.
Because of the time consumed to actually collect these samples, the large amount of processing required to identify early/late for each bit and whether the total of clocks were early or late, and the latencies of the various circuits of the system, the update rate and therefore the bandwidth of the CDR is limited. In addition, different industry standards and different applications require different amounts of clock recovery bandwidth or tracking capability. Accordingly, it would be desirable to have systems and/or methods that monitor and correct recovered clock(s) in order to facilitate improved clock and data recovery of incoming or received serial data streams while providing programmable bandwidth and tracking accuracy.